Infra · 28 May 2026 · 2 min read

Xcena raises 135M to tackle AI memory bottleneck

Chip startup XCENA's $135M Series B bets that memory, not compute, is AI's real bottleneck — a signal for builders planning future infrastructure.

Pen-and-ink illustration: a single, intricately carved key being. For the story "Xcena raises 135M to tackle AI memory bottleneck".
— Pen-and-ink illustration: a single, intricately carved key being. For the story "Xcena raises 135M to tackle AI memory bottleneck". —

What happened

XCENA, a four-year-old chip startup, has raised $135 million in a Series B round at a $570 million valuation. The funding, reported by TechCrunch, brings the company’s total raised to $185 million.

XCENA designs chips that move compute closer to DRAM memory, aiming to reduce the data-transfer bottleneck between CPUs, GPUs, and memory. The company's first chip, the MX1, is a prototype, with mass production planned for the end of 2026.

How the room's reading it

The raise is being framed as a bet on memory becoming the primary bottleneck for AI infrastructure, shifting focus from pure compute. Investors are backing the idea that bringing compute closer to data can unlock significant cost savings, especially for hyperscalers. This view is echoed by rising valuations for memory giants like Samsung and SK Hynix.

Some practitioners see this as a natural evolution. While GPUs handle the heavy maths of training, the data orchestration for inference — things like KV cache management — remains a costly problem. Competitors like Astera Labs and Marvell are also chasing this memory-connectivity space, suggesting a consensus is forming around the problem, even if the solutions differ.

Sailfish's take

We've seen this story before — a new chip promises to solve a fundamental bottleneck. The thesis that memory, not compute, is the next big problem for inference at scale feels correct. Moving data is expensive, and XCENA's approach of processing it near the source is the right instinct, representing a direct attack on the cost of running large models.

But we're not switching our infrastructure plans just yet. XCENA’s chip is still a prototype, with mass production two years away. We're watching this space closely, but for builders shipping today, the problem remains one of software optimisation on existing hardware. This is a trend to track, not a stack to adopt.

Our take — your read?

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Sources
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